TORC: torc/bitstream/OutputStreamHelpers.cpp Source File

00001 // Torc - Copyright 2011 University of Southern California.  All Rights Reserved.
00002 // $HeadURL: https://torc-isi.svn.sourceforge.net/svnroot/torc-isi/branches/staging/0.9/src/torc/bitstream/OutputStreamHelpers.cpp $
00003 // $Id: OutputStreamHelpers.cpp 10 2011-10-12 18:40:16Z nsteiner $
00004 
00005 // This program is free software: you can redistribute it and/or modify it under the terms of the 
00006 // GNU General Public License as published by the Free Software Foundation, either version 3 of the 
00007 // License, or (at your option) any later version.
00008 // 
00009 // This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; 
00010 // without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See 
00011 // the GNU General Public License for more details.
00012 // 
00013 // You should have received a copy of the GNU General Public License along with this program.  If 
00014 // not, see <http://www.gnu.org/licenses/>.
00015 
00016 /// \file
00017 /// \brief Source for torc::bitstream output stream helpers.
00018 
00019 #include "torc/bitstream/OutputStreamHelpers.hpp"
00020 #include "torc/bitstream/Bitstream.hpp"
00021 #include "torc/bitstream/Virtex.hpp"
00022 #include "torc/bitstream/VirtexE.hpp"
00023 #include "torc/bitstream/Virtex2.hpp"
00024 #include "torc/bitstream/Virtex2P.hpp"
00025 #include "torc/bitstream/Virtex4.hpp"
00026 #include "torc/bitstream/Virtex5.hpp"
00027 #include "torc/bitstream/Virtex6.hpp"
00028 #include "torc/bitstream/Virtex7.hpp"
00029 #include "torc/bitstream/VirtexPacket.hpp"
00030 #include "torc/bitstream/Spartan3E.hpp"
00031 #include "torc/bitstream/Spartan6.hpp"
00032 #include "torc/bitstream/SpartanPacket.hpp"
00033 #include "torc/bitstream/Spartan6Packet.hpp"
00034 #include "torc/bitstream/Spartan6Bitstream.hpp"
00035 #include <iostream>
00036 #include <iomanip>
00037 
00038 namespace torc {
00039 namespace bitstream {
00040 
00041     std::ostream& operator <<(std::ostream& os, const Hex16& inWord) {
00042         return os << std::hex << std::setfill('0') << std::setw(8) << inWord.mWord << std::dec;
00043     }
00044 
00045     std::ostream& operator <<(std::ostream& os, const Hex32& inWord) {
00046         return os << std::hex << std::setfill('0') << std::setw(8) << inWord.mWord << std::dec;
00047     }
00048 
00049     std::ostream& operator <<(std::ostream& os, const Bitstream& rhs) {
00050         // dispatch the various architectures
00051         if(typeid(rhs) == typeid(Virtex)) {
00052             os << dynamic_cast<const Virtex&>(rhs);
00053         } else if(typeid(rhs) == typeid(VirtexE)) {
00054             os << dynamic_cast<const VirtexE&>(rhs);
00055         } else if(typeid(rhs) == typeid(Virtex2)) {
00056             os << dynamic_cast<const Virtex2&>(rhs);
00057         } else if(typeid(rhs) == typeid(Virtex2P)) {
00058             os << dynamic_cast<const Virtex2P&>(rhs);
00059         } else if(typeid(rhs) == typeid(Virtex4)) {
00060             os << dynamic_cast<const Virtex4&>(rhs);
00061         } else if(typeid(rhs) == typeid(Virtex5)) {
00062             os << dynamic_cast<const Virtex5&>(rhs);
00063         } else if(typeid(rhs) == typeid(Virtex6)) {
00064             os << dynamic_cast<const Virtex6&>(rhs);
00065         } else if(typeid(rhs) == typeid(Virtex7)) {
00066             os << dynamic_cast<const Virtex7&>(rhs);
00067         } else if(typeid(rhs) == typeid(Spartan3E)) {
00068             os << dynamic_cast<const Spartan3E&>(rhs);
00069         } else if(typeid(rhs) == typeid(Spartan6)) {
00070             os << dynamic_cast<const Spartan6&>(rhs);
00071 
00072         // handle the generic bitstream header
00073         } else {
00074             os << "Design " << rhs.mDesignName << " (" << rhs.mDeviceName << ") @ " 
00075             << rhs.mDesignDate << " " << rhs.mDesignTime << ": " << rhs.mBitstreamByteLength 
00076             << " bytes (" << (rhs.mBitstreamByteLength >> 2) << " words)";
00077         }
00078         return os;
00079     }
00080 
00081     std::ostream& operator <<(std::ostream& os, const Spartan6Bitstream& rhs) {
00082         return os << "Design " << rhs.mDesignName << " (" << rhs.mDeviceName << ") @ " 
00083             << rhs.mDesignDate << " " << rhs.mDesignTime << ": " << rhs.mBitstreamByteLength 
00084             << " bytes (" << (rhs.mBitstreamByteLength >> 1) << " words)";
00085     }
00086 
00087     // Spartan3E Output Stream
00088     std::ostream& operator <<(std::ostream& os, const Spartan3E& rhs) {
00089         // insert the bitstream header
00090         os << static_cast<const Bitstream>(rhs) << std::endl;
00091         uint32_t cumulativeWordLength = 0;
00092         bool newColumn = false;
00093         bool newBlock = false;
00094         uint32_t oldColumnValue = 0;
00095         uint32_t oldBlockValue = 0;
00096         uint32_t currentColumnValue = 0;
00097         uint32_t currentBlockValue = 0;
00098 
00099         // iterate over the packets
00100         Spartan3E::ERegister address = Spartan3E::ERegister();
00101         //SpartanPacketVector::const_iterator p = rhs.begin();
00102         std::vector<SpartanPacket>::const_iterator p = rhs.begin();
00103         //SpartanPacketVector::const_iterator e = rhs.end();
00104         std::vector<SpartanPacket>::const_iterator e = rhs.end();
00105         while(p < e) {
00106 
00107             // insert the byte address
00108             os << "    " << Hex32(rhs.getHeaderByteLength() + (cumulativeWordLength << 2)) << ": ";
00109             // look up the packet
00110             const SpartanPacket& packet = *p++;
00111             cumulativeWordLength += packet.getWordSize();
00112 
00113             // handle dummy words
00114             if(packet.isDummyWord()) {
00115                 os << "DUMMY" << std::endl;
00116 
00117             // handle sync words
00118             } else if(packet.isSyncWord()) {
00119                 os << "SYNC" << std::endl;
00120 
00121             // handle reserved packets
00122             } else if(packet.isReserved()) {
00123                 os << Spartan3E::sOpcodeName[packet.getOpcode()] << std::endl;
00124             
00125             // handle NOP packets
00126             } else if(packet.isNop()) {
00127                 int nops = 1;
00128                 while(p < e && p->isNop()) { nops++; p++; }
00129                 cumulativeWordLength += nops - 1;
00130                 os << "NOP x " << nops << std::endl;
00131 
00132             // handle regular type 1 or type 2 packets
00133             } else {
00134 
00135                 // look up the packet details
00136                 Spartan3E::EPacketType type = packet.getType();
00137                 Spartan3E::EOpcode opcode = packet.getOpcode();
00138                 uint32_t wordCount = packet.getWordCount();
00139                 const uint32_t word = packet[1];
00140 
00141                 // account for the packet type
00142                 os << Spartan3E::sPacketTypeName[type];
00143                 switch(type) {
00144                 case Spartan3E::ePacketType1: 
00145                     address = Spartan3E::ERegister(packet.getAddress());
00146                     break;
00147                 case Spartan3E::ePacketType2: 
00148                     break;
00149                 default: 
00150                     os << std::endl;
00151                     continue;
00152                 }
00153 
00154                 // handle read packets
00155                 if(opcode == packet.isRead()) {
00156                     os << " READ " << Spartan3E::sRegisterName[address];
00157 
00158                 // handle write packets
00159                 } else if(opcode == Spartan3E::eOpcodeWrite) {
00160                     os << " WRITE " << Spartan3E::sRegisterName[address];
00161                     // process according to register address
00162                     switch(address) {
00163                     case Spartan3E::eRegisterFDRI:
00164                         os << ": " << Hex32(wordCount) << " words";
00165                         break;
00166                     case Spartan3E::eRegisterCMD: 
00167                         os << " " << Spartan3E::sCommandName[word];
00168                         break;
00169                     case Spartan3E::eRegisterCOR:
00170                         os << ": " << Hex32(word);
00171                         Spartan3E::writeSubfieldSettings(os, uint32_t(word), Spartan3E::sCOR);
00172                         break;
00173                     case Spartan3E::eRegisterSTAT:
00174                         os << ": " << Hex32(word);
00175                         Spartan3E::writeSubfieldSettings(os, uint32_t(word), Spartan3E::sSTAT);
00176                         break;
00177                     case Spartan3E::eRegisterCTL:
00178                         os << ": " << Hex32(word);
00179                         Spartan3E::writeSubfieldSettings(os, uint32_t(word), Spartan3E::sCTL);
00180                         break;
00181                     case Spartan3E::eRegisterMASK:
00182                         os << ": " << Hex32(word);
00183                         Spartan3E::writeSubfieldSettings(os, uint32_t(word), Spartan3E::sMASK);
00184                         break;
00185                     // Added to make frame mapping debug easier
00186                     case Spartan3E::eRegisterLOUT:
00187                         oldColumnValue = currentColumnValue;
00188                         oldBlockValue = currentBlockValue;
00189                         currentColumnValue = (word & Virtex::eFarMaskMajor);
00190                         currentBlockValue = (word & Virtex::eFarMaskBlockType);
00191                         newColumn = (currentColumnValue != oldColumnValue);
00192                         newBlock = (currentBlockValue != oldBlockValue);
00193                         os << ": " << Hex32(word);
00194                         if(newColumn) std::cout << "\t\t\t!!!New Column!!!";
00195                         if(newBlock) std::cout << "\t\t\t\t\t***New Block***" << Hex32(currentBlockValue);
00196                         break;
00197                     default:
00198                         // output the register contents
00199                         os << ": " << Hex32(word);
00200                         break;
00201                     }
00202                     os << std::endl;
00203                 }
00204 
00205             }
00206 
00207         }
00208 
00209         // return the stream reference
00210         return os;
00211     }
00212 
00213 
00214     // Spartan6 Output Stream
00215     std::ostream& operator <<(std::ostream& os, const Spartan6& rhs) {
00216         // insert the bitstream header
00217         // be careful to cast this as a Spartan6Bitstream, rather than an ordinary Bitstream
00218         os << static_cast<const Spartan6Bitstream>(rhs) << std::endl;
00219         uint32_t cumulativeWordLength = 0;
00220 
00221         // iterate over the packets
00222         Spartan6::ERegister address = Spartan6::ERegister();
00223         //SpartanPacketVector::const_iterator p = rhs.begin();
00224         std::vector<Spartan6Packet>::const_iterator p = rhs.begin();
00225         //SpartanPacketVector::const_iterator e = rhs.end();
00226         std::vector<Spartan6Packet>::const_iterator e = rhs.end();
00227         while(p < e) {
00228 
00229             // insert the byte address
00230             os << "    " << Hex32(rhs.getHeaderByteLength() + (cumulativeWordLength << 1)) << ": ";
00231             // look up the packet
00232             const Spartan6Packet& packet = *p++;
00233             cumulativeWordLength += packet.getWordSize();
00234 
00235             // handle dummy words
00236             if(packet.isDummyWord()) {
00237                 os << "DUMMY" << std::endl;
00238 
00239             // handle sync words
00240             } else if(packet.isSyncWord0()) {
00241                 os << "SYNC0" << std::endl;
00242 
00243                 // handle sync words
00244             } else if(packet.isSyncWord1()) {
00245                 os << "SYNC1" << std::endl;
00246 
00247             // handle reserved packets
00248             } else if(packet.isReserved()) {
00249                 os << Spartan6::sOpcodeName[packet.getOpcode()] << std::endl;
00250             
00251             // handle NOP packets
00252             } else if(packet.isNop()) {
00253                 int nops = 1;
00254                 while(p < e && p->isNop()) { nops++; p++; }
00255                 cumulativeWordLength += nops - 1;
00256                 os << "NOP x " << nops << std::endl;
00257 
00258             // handle regular type 1 or type 2 packets
00259             } else {
00260 
00261                 // look up the packet details
00262                 Spartan6::EPacketType type = packet.getType();
00263                 Spartan6::EOpcode opcode = packet.getOpcode();
00264                 uint32_t wordCount = packet.getWordCount();
00265                 const uint16_t word = packet[1];
00266                 const uint32_t word32 = (packet[1] << 16) | packet[2];
00267 
00268                 // account for the packet type
00269                 os << Spartan6::sPacketTypeName[type];
00270                 switch(type) {
00271                 case Spartan6::ePacketType1: 
00272                 case Spartan6::ePacketType2: 
00273                     address = Spartan6::ERegister(packet.getAddress());
00274                     break;
00275                 default: 
00276                     os << std::endl;
00277                     continue;
00278                 }
00279 
00280                 // handle read packets
00281                 if(opcode == packet.isRead()) {
00282                     os << " READ " << Spartan6::sRegisterName[address];
00283 
00284                 // handle write packets
00285                 } else if(opcode == Spartan6::eOpcodeWrite) {
00286                     os << " WRITE " << Spartan6::sRegisterName[address];
00287                     // process according to register address
00288                     switch(address) {
00289                     case Spartan6::eRegisterCMD: 
00290                         os << " " << Spartan6::sCommandName[word];
00291                         break;
00292                     case Spartan6::eRegisterCOR1:
00293                         os << ": " << Hex16(word);
00294                         Spartan6::writeSubfieldSettings(os, uint16_t(word), Spartan6::sCOR1);
00295                         break;
00296                     case Spartan6::eRegisterCOR2:
00297                         os << ": " << Hex16(word);
00298                         Spartan6::writeSubfieldSettings(os, uint16_t(word), Spartan6::sCOR2);
00299                         break;
00300                     case Spartan6::eRegisterSTAT:
00301                         os << ": " << Hex16(word);
00302                         Spartan6::writeSubfieldSettings(os, uint16_t(word), Spartan6::sSTAT);
00303                         break;
00304                     case Spartan6::eRegisterCTL:
00305                         os << ": " << Hex16(word);
00306                         Spartan6::writeSubfieldSettings(os, uint16_t(word), Spartan6::sCTL);
00307                         break;
00308                     case Spartan6::eRegisterMASK:
00309                         os << ": " << Hex16(word);
00310                         Spartan6::writeSubfieldSettings(os, uint16_t(word), Spartan6::sMASK);
00311                         break;
00312                     case Spartan6::eRegisterPWRDN_REG:
00313                         os << ": " << Hex16(word);
00314                         Spartan6::writeSubfieldSettings(os, uint16_t(word), Spartan6::sPWRDN_REG);
00315                         break;
00316                     case Spartan6::eRegisterHC_OPT_REG:
00317                         os << ": " << Hex16(word);
00318                         Spartan6::writeSubfieldSettings(os, uint16_t(word), Spartan6::sHC_OPT_REG);
00319                         break;
00320                     case Spartan6::eRegisterMODE_REG:
00321                         os << ": " << Hex16(word);
00322                         Spartan6::writeSubfieldSettings(os, uint16_t(word), Spartan6::sMODE_REG);
00323                         break;
00324                     case Spartan6::eRegisterBOOSTS:
00325                         os << ": " << Hex16(word);
00326                         Spartan6::writeSubfieldSettings(os, uint16_t(word), Spartan6::sBOOSTS);
00327                         break;
00328                     case Spartan6::eRegisterSEU_OPT:
00329                         os << ": " << Hex16(word);
00330                         Spartan6::writeSubfieldSettings(os, uint16_t(word), Spartan6::sSEU_OPT);
00331                         break;
00332                     case Spartan6::eRegisterRDBK_SIGN:
00333                         os << ": " << Hex32(word32);
00334                         break;
00335                     case Spartan6::eRegisterIDCODE:
00336                         os << ": " << Hex32(word32);
00337                         break;
00338                     case Spartan6::eRegisterCRC:
00339                         os << ": " << Hex32(word32);
00340                         break;
00341                     case Spartan6::eRegisterFDRI:
00342                     //    if(packet.hasAutoCRC())
00343                     //  {
00344                     //    os << ": " << Hex32(wordCount) << " words\n";
00345                     //    os << "\t\t\t\tAUTOCRC: " << Hex32(packet.getAutoCRC());
00346                     //  }
00347                     //  else
00348                           os << ": " << Hex32(wordCount) << " words\n";
00349                         break;
00350                     case Spartan6::eRegisterFARMAJ:
00351                         // Only updates the FAR Major
00352                         if (wordCount == 1)
00353                           os << "Major Address: " << Hex16(packet[1]);
00354                         // Updates both the FAR Major and Minor address
00355                         // Word 1: FAR Major
00356                         // Word 2: FAR Minor
00357                         else if (wordCount == 2) {
00358                           std::cout << std::endl;
00359                           os << "\t\t\t\tMajor Address: " << Hex16(packet[1]);
00360                           std::cout << std::endl;
00361                           os << "\t\t\t\tMinor Address: " << Hex16(packet[2] >> 1);
00362                         }
00363                         break;
00364                     default:
00365                         // output the register contents
00366                         os << ": " << Hex16(word);
00367                         break;
00368                     }
00369                     os << std::endl;
00370                 }
00371 
00372             }
00373 
00374         }
00375 
00376         // return the stream reference
00377         return os;
00378     }
00379 
00380 
00381     // Virtex Output Stream
00382     std::ostream& operator <<(std::ostream& os, const Virtex& rhs) {
00383         // insert the bitstream header
00384         os << static_cast<const Bitstream>(rhs) << std::endl;
00385         uint32_t cumulativeWordLength = 0;
00386         bool newColumn = false;
00387         bool newBlock = false;
00388         uint32_t oldColumnValue = 0;
00389         uint32_t oldBlockValue = 0;
00390         uint32_t currentColumnValue = 0;
00391         uint32_t currentBlockValue = 0;
00392 
00393         // iterate over the packets
00394         Virtex::ERegister address = Virtex::ERegister();
00395         VirtexPacketVector::const_iterator p = rhs.begin();
00396         VirtexPacketVector::const_iterator e = rhs.end();
00397         while(p < e) {
00398 
00399             // insert the byte address
00400             os << "    " << Hex32(rhs.getHeaderByteLength() + (cumulativeWordLength << 2)) << ": ";
00401             // look up the packet
00402             const VirtexPacket& packet = *p++;
00403             cumulativeWordLength += packet.getWordSize();
00404 
00405             // handle dummy words
00406             if(packet.isDummyWord()) {
00407                 os << "DUMMY" << std::endl;
00408 
00409             // handle sync words
00410             } else if(packet.isSyncWord()) {
00411                 os << "SYNC" << std::endl;
00412 
00413             // handle reserved packets
00414             } else if(packet.isReserved()) {
00415                 os << Virtex::sOpcodeName[packet.getOpcode()] << std::endl;
00416             
00417             /* Not used in Virtex
00418             // handle NOP packets
00419             } else if(packet.isNop()) {
00420                 int nops = 1;
00421                 while(p < e && p->isNop()) { nops++; p++; }
00422                 cumulativeWordLength += nops - 1;
00423                 os << "NOP x " << nops << std::endl;
00424             */
00425 
00426             // handle regular type 1 or type 2 packets
00427             } else {
00428 
00429                 // look up the packet details
00430                 Virtex::EPacketType type = packet.getType();
00431                 Virtex::EOpcode opcode = packet.getOpcode();
00432                 uint32_t wordCount = packet.getWordCount();
00433                 const uint32_t word = packet[1];
00434 
00435                 // account for the packet type
00436                 os << Virtex::sPacketTypeName[type];
00437                 switch(type) {
00438                 case Virtex::ePacketType1: 
00439                     address = Virtex::ERegister(packet.getAddress());
00440                     break;
00441                 case Virtex::ePacketType2: 
00442                     break;
00443                 default: 
00444                     os << std::endl;
00445                     continue;
00446                 }
00447 
00448                 // handle read packets
00449                 if(opcode == packet.isRead()) {
00450                     os << " READ " << Virtex::sRegisterName[address];
00451 
00452                 // handle write packets
00453                 } else if(opcode == Virtex::eOpcodeWrite) {
00454                     os << " WRITE " << Virtex::sRegisterName[address];
00455                     // process according to register address
00456                     switch(address) {
00457                     case Virtex::eRegisterFDRI:
00458                         os << ": " << Hex32(wordCount) << " words";
00459                         break;
00460                     case Virtex::eRegisterCMD: 
00461                         os << " " << Virtex::sCommandName[word];
00462                         break;
00463                     case Virtex::eRegisterCOR:
00464                         os << ": " << Hex32(word);
00465                         Virtex::writeSubfieldSettings(os, uint32_t(word), Virtex::sCOR);
00466                         break;
00467                     case Virtex::eRegisterSTAT:
00468                         os << ": " << Hex32(word);
00469                         Virtex::writeSubfieldSettings(os, uint32_t(word), Virtex::sSTAT);
00470                         break;
00471                     case Virtex::eRegisterCTL:
00472                         os << ": " << Hex32(word);
00473                         Virtex::writeSubfieldSettings(os, uint32_t(word), Virtex::sCTL);
00474                         break;
00475                     case Virtex::eRegisterMASK:
00476                         os << ": " << Hex32(word);
00477                         Virtex::writeSubfieldSettings(os, uint32_t(word), Virtex::sMASK);
00478                         break;
00479                     // Added to make frame mapping debug easier
00480                     case Virtex::eRegisterLOUT:
00481                         oldColumnValue = currentColumnValue;
00482                         oldBlockValue = currentBlockValue;
00483                         currentColumnValue = (word & Virtex::eFarMaskMajor);
00484                         currentBlockValue = (word & Virtex::eFarMaskBlockType);
00485                         newColumn = (currentColumnValue != oldColumnValue);
00486                         newBlock = (currentBlockValue != oldBlockValue);
00487                         os << ": " << Hex32(word);
00488                         if(newColumn) std::cout << "\t\t\t!!!New Column!!!";
00489                         if(newBlock) std::cout << "\t\t\t\t\t***New Block***" << Hex32(currentBlockValue);
00490                         break;
00491                     default:
00492                         // output the register contents
00493                         os << ": " << Hex32(word);
00494                         break;
00495                     }
00496                     os << std::endl;
00497                 }
00498 
00499             }
00500 
00501         }
00502 
00503         // return the stream reference
00504         return os;
00505     }
00506 
00507 
00508     // Virtex2 Output Stream
00509     std::ostream& operator <<(std::ostream& os, const Virtex2& rhs) {
00510         // insert the bitstream header
00511         os << static_cast<const Bitstream>(rhs) << std::endl;
00512         uint32_t cumulativeWordLength = 0;
00513 
00514         // iterate over the packets
00515         Virtex2::ERegister address = Virtex2::ERegister();
00516         VirtexPacketVector::const_iterator p = rhs.begin();
00517         VirtexPacketVector::const_iterator e = rhs.end();
00518         bool newColumn = false;
00519         bool newBlock = false;
00520         uint32_t oldColumnValue = 0;
00521         uint32_t oldBlockValue = 0;
00522         uint32_t currentColumnValue = 0;
00523         uint32_t currentBlockValue = 0;
00524         while(p < e) {
00525 
00526             // insert the byte address
00527             os << "    " << Hex32(rhs.getHeaderByteLength() + (cumulativeWordLength << 2)) << ": ";
00528             // look up the packet
00529             const VirtexPacket& packet = *p++;
00530             cumulativeWordLength += packet.getWordSize();
00531 
00532             // handle dummy words
00533             if(packet.isDummyWord()) {
00534                 os << "DUMMY" << std::endl;
00535 
00536             // handle sync words
00537             } else if(packet.isSyncWord()) {
00538                 os << "SYNC" << std::endl;
00539 
00540             // handle reserved packets
00541             } else if(packet.isReserved()) {
00542                 os << Virtex2::sOpcodeName[packet.getOpcode()] << std::endl;
00543 
00544             // handle NOP packets
00545             } else if(packet.isNop()) {
00546                 int nops = 1;
00547                 while(p < e && p->isNop()) { nops++; p++; }
00548                 cumulativeWordLength += nops - 1;
00549                 os << "NOP x " << nops << std::endl;
00550 
00551             // handle regular type 1 or type 2 packets
00552             } else {
00553 
00554                 // look up the packet details
00555                 Virtex2::EPacketType type = packet.getType();
00556                 Virtex2::EOpcode opcode = packet.getOpcode();
00557                 uint32_t wordCount = packet.getWordCount();
00558                 const uint32_t word = packet[1];
00559 
00560                 // account for the packet type
00561                 os << Virtex2::sPacketTypeName[type];
00562                 switch(type) {
00563                 case Virtex2::ePacketType1: 
00564                     address = Virtex2::ERegister(packet.getAddress());
00565                     break;
00566                 case Virtex2::ePacketType2: 
00567                     break;
00568                 default: 
00569                     os << std::endl;
00570                     continue;
00571                 }
00572 
00573                 // handle read packets
00574                 if(opcode == packet.isRead()) {
00575                     os << " READ " << Virtex2::sRegisterName[address];
00576 
00577                 // handle write packets
00578                 } else if(opcode == Virtex2::eOpcodeWrite) {
00579                     os << " WRITE " << Virtex2::sRegisterName[address];
00580                     // process according to register address
00581                     switch(address) {
00582                     case Virtex2::eRegisterFDRI:
00583                         os << ": " << Hex32(wordCount) << " words";
00584                         break;
00585                     case Virtex2::eRegisterCMD: 
00586                         os << " " << Virtex2::sCommandName[word];
00587                         break;
00588                     case Virtex2::eRegisterCOR:
00589                         os << ": " << Hex32(word);
00590                         Virtex2::writeSubfieldSettings(os, uint32_t(word), Virtex2::sCOR);
00591                         break;
00592                     case Virtex2::eRegisterSTAT:
00593                         os << ": " << Hex32(word);
00594                         Virtex2::writeSubfieldSettings(os, uint32_t(word), Virtex2::sSTAT);
00595                         break;
00596                     case Virtex2::eRegisterCTL:
00597                         os << ": " << Hex32(word);
00598                         Virtex2::writeSubfieldSettings(os, uint32_t(word), Virtex2::sCTL);
00599                         break;
00600                     case Virtex2::eRegisterMASK:
00601                         os << ": " << Hex32(word);
00602                         Virtex2::writeSubfieldSettings(os, uint32_t(word), Virtex2::sMASK);
00603                         break;
00604                     // Added to make frame mapping debug easier
00605                     case Virtex2::eRegisterLOUT:
00606                         oldColumnValue = currentColumnValue;
00607                         oldBlockValue = currentBlockValue;
00608                         currentColumnValue = (word & Virtex2::eFarMaskMajor);
00609                         currentBlockValue = (word & Virtex2::eFarMaskBlockType);
00610                         newColumn = (currentColumnValue != oldColumnValue);
00611                         newBlock = (currentBlockValue != oldBlockValue);
00612                         os << ": " << Hex32(word);
00613                         if(newColumn) std::cout << "\t\t\t!!!New Column!!!";
00614                         if(newBlock) std::cout << "\t\t\t\t\t***New Block***" << Hex32(currentBlockValue);
00615                         break;
00616                     default:
00617                         // output the register contents
00618                         os << ": " << Hex32(word);
00619                         break;
00620                     }
00621                     os << std::endl;
00622                 }
00623 
00624             }
00625 
00626         }
00627 
00628         // return the stream reference
00629         return os;
00630     }
00631 
00632 
00633     // Virtex4 Output Stream
00634     std::ostream& operator <<(std::ostream& os, const Virtex4& rhs) {
00635         // insert the bitstream header
00636         os << static_cast<const Bitstream>(rhs) << std::endl;
00637         uint32_t cumulativeWordLength = 0;
00638 
00639         // iterate over the packets
00640         Virtex4::ERegister address = Virtex4::ERegister();
00641         VirtexPacketVector::const_iterator p = rhs.begin();
00642         VirtexPacketVector::const_iterator e = rhs.end();
00643         bool newColumn = false;
00644         bool newRow = false;
00645         bool newTop = false;
00646         bool newBlock = false;
00647         uint32_t oldColumnValue = 0;
00648         uint32_t oldRowValue = 0;
00649         uint32_t oldTopValue = 0;
00650         uint32_t oldBlockValue = 0;
00651         uint32_t currentColumnValue = 0;
00652         uint32_t currentRowValue = 0;
00653         uint32_t currentTopValue = 0;
00654         uint32_t currentBlockValue = 0;
00655         while(p < e) {
00656 
00657             // insert the byte address
00658             os << "    " << Hex32(rhs.getHeaderByteLength() + (cumulativeWordLength << 2)) << ": ";
00659             // look up the packet
00660             const VirtexPacket& packet = *p++;
00661             cumulativeWordLength += packet.getWordSize();
00662 
00663             // handle dummy words
00664             if(packet.isDummyWord()) {
00665                 os << "DUMMY" << std::endl;
00666 
00667             // handle sync words
00668             } else if(packet.isSyncWord()) {
00669                 os << "SYNC" << std::endl;
00670 
00671             // handle reserved packets
00672             } else if(packet.isReserved()) {
00673                 os << Virtex4::sOpcodeName[packet.getOpcode()] << std::endl;
00674 
00675             // handle NOP packets
00676             } else if(packet.isNop()) {
00677                 int nops = 1;
00678                 while(p < e && p->isNop()) { nops++; p++; }
00679                 cumulativeWordLength += nops - 1;
00680                 os << "NOP x " << nops << std::endl;
00681 
00682             // handle regular type 1 or type 2 packets
00683             } else {
00684 
00685                 // look up the packet details
00686                 Virtex4::EPacketType type = packet.getType();
00687                 Virtex4::EOpcode opcode = packet.getOpcode();
00688                 uint32_t wordCount = packet.getWordCount();
00689                 const uint32_t word = packet[1];
00690 
00691                 // account for the packet type
00692                 os << Virtex4::sPacketTypeName[type];
00693                 switch(type) {
00694                 case Virtex4::ePacketType1: 
00695                     address = Virtex4::ERegister(packet.getAddress());
00696                     break;
00697                 case Virtex4::ePacketType2: 
00698                     break;
00699                 default: 
00700                     os << std::endl;
00701                     continue;
00702                 }
00703 
00704                 // handle read packets
00705                 if(opcode == packet.isRead()) {
00706                     os << " READ " << Virtex4::sRegisterName[address];
00707 
00708                 // handle write packets
00709                 } else if(opcode == Virtex4::eOpcodeWrite) {
00710                     os << " WRITE " << Virtex4::sRegisterName[address];
00711                     // process according to register address
00712                     switch(address) {
00713                     case Virtex4::eRegisterFDRI:
00714                         os << ": " << Hex32(wordCount) << " words";
00715                         break;
00716                     case Virtex4::eRegisterCMD: 
00717                         os << " " << Virtex4::sCommandName[word];
00718                         break;
00719                     case Virtex4::eRegisterCOR:
00720                         os << ": " << Hex32(word);
00721                         Virtex4::writeSubfieldSettings(os, uint32_t(word), Virtex4::sCOR);
00722                         break;
00723                     case Virtex4::eRegisterSTAT:
00724                         os << ": " << Hex32(word);
00725                         Virtex4::writeSubfieldSettings(os, uint32_t(word), Virtex4::sSTAT);
00726                         break;
00727                     case Virtex4::eRegisterCTL:
00728                         os << ": " << Hex32(word);
00729                         Virtex4::writeSubfieldSettings(os, uint32_t(word), Virtex4::sCTL);
00730                         break;
00731                     case Virtex4::eRegisterMASK:
00732                         os << ": " << Hex32(word);
00733                         Virtex4::writeSubfieldSettings(os, uint32_t(word), Virtex4::sMASK);
00734                         break;
00735                     // Added to make frame mapping debug easier
00736                     case Virtex4::eRegisterLOUT:
00737                         oldColumnValue = currentColumnValue;
00738                         oldRowValue = currentRowValue;
00739                         oldTopValue = currentTopValue;
00740                         oldBlockValue = currentBlockValue;
00741                         currentColumnValue = (word & Virtex6::eFarMaskMajor);
00742                         currentRowValue = (word & Virtex6::eFarMaskRow);
00743                         currentTopValue = (word & Virtex6::eFarMaskTopBottom);
00744                         currentBlockValue = (word & Virtex6::eFarMaskBlockType);
00745                         newColumn = (currentColumnValue != oldColumnValue);
00746                         newRow = (currentRowValue != oldRowValue);
00747                         newTop = (currentTopValue != oldTopValue);
00748                         newBlock = (currentBlockValue != oldBlockValue);
00749                         os << ": " << Hex32(word);
00750                         if(newColumn) std::cout << "\t\t\t!!!New Column!!!";
00751                         if(newRow) std::cout << "\t\t\t$$$New Row$$$";
00752                         if(newTop) std::cout << "\t\t\t&&&New Top&&&";
00753                         if(newBlock) std::cout << "\t\t\t\t\t***New Block***" << Hex32(currentBlockValue);
00754                         break;
00755                     default:
00756                         // output the register contents
00757                         os << ": " << Hex32(word);
00758                         break;
00759                     }
00760                     os << std::endl;
00761                 }
00762 
00763             }
00764 
00765         }
00766 
00767         // return the stream reference
00768         return os;
00769     }
00770 
00771     // Virtex5 Output Stream
00772     std::ostream& operator <<(std::ostream& os, const Virtex5& rhs) {
00773         // insert the bitstream header
00774         os << static_cast<const Bitstream>(rhs) << std::endl;
00775         uint32_t cumulativeWordLength = 0;
00776 
00777         // iterate over the packets
00778         Virtex5::ERegister address = Virtex5::ERegister();
00779         VirtexPacketVector::const_iterator p = rhs.begin();
00780         VirtexPacketVector::const_iterator e = rhs.end();
00781         bool synchronized = false;
00782         bool newColumn = false;
00783         bool newRow = false;
00784         bool newTop = false;
00785         bool newBlock = false;
00786         uint32_t oldColumnValue = 0;
00787         uint32_t oldRowValue = 0;
00788         uint32_t oldTopValue = 0;
00789         uint32_t oldBlockValue = 0;
00790         uint32_t currentColumnValue = 0;
00791         uint32_t currentRowValue = 0;
00792         uint32_t currentTopValue = 0;
00793         uint32_t currentBlockValue = 0;
00794         while(p < e) {
00795 
00796             // insert the byte address
00797             os << "    " << Hex32(rhs.getHeaderByteLength() + (cumulativeWordLength << 2)) << ": ";
00798             // look up the packet
00799             const VirtexPacket& packet = *p++;
00800             cumulativeWordLength += packet.getWordSize();
00801 
00802             // catch bus sync words
00803             if(!synchronized) {
00804                 if(packet.isBusWidthSyncWord()) {
00805                     os << "BUS WIDTH SYNC" << std::endl;
00806                     continue;
00807                 } else if(packet.isBusWidthDetectWord()) {
00808                     os << "BUS WIDTH DETECT" << std::endl;
00809                     continue;
00810                 }
00811             }
00812 
00813             // handle dummy words
00814             if(packet.isDummyWord()) {
00815                 os << "DUMMY" << std::endl;
00816 
00817             // handle sync words
00818             } else if(packet.isSyncWord()) {
00819                 os << "SYNC" << std::endl;
00820 
00821             // handle reserved packets
00822             } else if(packet.isReserved()) {
00823                 os << Virtex5::sOpcodeName[packet.getOpcode()] << std::endl;
00824 
00825             // handle NOP packets
00826             } else if(packet.isNop()) {
00827                 int nops = 1;
00828                 while(p < e && p->isNop()) { nops++; p++; }
00829                 cumulativeWordLength += nops - 1;
00830                 os << "NOP x " << nops << std::endl;
00831 
00832             // handle regular type 1 or type 2 packets
00833             } else {
00834 
00835                 // look up the packet details
00836                 Virtex5::EPacketType type = packet.getType();
00837                 Virtex5::EOpcode opcode = packet.getOpcode();
00838                 uint32_t wordCount = packet.getWordCount();
00839                 const uint32_t word = packet[1];
00840                 // account for the packet type
00841                 os << Virtex5::sPacketTypeName[type];
00842                 switch(type) {
00843                 case Virtex5::ePacketType1: 
00844                     address = Virtex5::ERegister(packet.getAddress());
00845                     break;
00846                 case Virtex5::ePacketType2: 
00847                     break;
00848                 default: 
00849                     os << std::endl;
00850                     continue;
00851                 }
00852 
00853                 // handle read packets
00854                 if(opcode == packet.isRead()) {
00855                     os << " READ " << Virtex5::sRegisterName[address];
00856 
00857                 // handle write packets
00858                 } else if(opcode == Virtex5::eOpcodeWrite) {
00859                     os << " WRITE " << Virtex5::sRegisterName[address];
00860                     // process according to register address
00861                     switch(address) {
00862                     case Virtex5::eRegisterFDRI:
00863                         os << ": " << Hex32(wordCount) << " words";
00864                         break;
00865                     case Virtex5::eRegisterCMD: 
00866                         os << " " << Virtex5::sCommandName[word];
00867                         break;
00868                     case Virtex5::eRegisterCOR0:
00869                         os << ": " << Hex32(word);
00870                         Virtex5::writeSubfieldSettings(os, (uint32_t) word, Virtex5::sCOR0);
00871                         break;
00872                     case Virtex5::eRegisterCOR1:
00873                         os << ": " << Hex32(word);
00874                         Virtex5::writeSubfieldSettings(os, (uint32_t) word, Virtex5::sCOR1);
00875                         break;
00876                     case Virtex5::eRegisterSTAT:
00877                         os << ": " << Hex32(word);
00878                         Virtex5::writeSubfieldSettings(os, (uint32_t) word, Virtex5::sSTAT);
00879                         break;
00880                     case Virtex5::eRegisterCTL0:
00881                         os << ": " << Hex32(word);
00882                         Virtex5::writeSubfieldSettings(os, (uint32_t) word, Virtex5::sCTL0);
00883                         break;
00884                     case Virtex5::eRegisterCTL1:
00885                         os << ": " << Hex32(word);
00886                         Virtex5::writeSubfieldSettings(os, (uint32_t) word, Virtex5::sCTL1);
00887                         break;
00888                     case Virtex5::eRegisterMASK:
00889                         os << ": " << Hex32(word);
00890                         // we need to snoop the next packet, because the documented mask subfields 
00891                         // apply to CTL0 only, and not to CTL1 which is completely undefined
00892                         if(p < e) {
00893                             const VirtexPacket& nextPacket = *p;
00894                             if(nextPacket.isType1() && nextPacket.isWrite() 
00895                                 && nextPacket.getAddress() == Virtex5::eRegisterCTL1) {
00896                                 os << " ()";
00897                                 break;
00898                             }
00899                         }
00900                         Virtex5::writeSubfieldSettings(os, (uint32_t) word, Virtex5::sMASK0);
00901                         break;
00902                     case Virtex5::eRegisterWBSTAR:
00903                         os << ": " << Hex32(word);
00904                         Virtex5::writeSubfieldSettings(os, (uint32_t) word, Virtex5::sWBSTAR);
00905                         break;
00906                     case Virtex5::eRegisterTIMER:
00907                         os << ": " << Hex32(word);
00908                         Virtex5::writeSubfieldSettings(os, (uint32_t) word, Virtex5::sTIMER);
00909                         break;
00910                     // Added to make frame mapping debug easier
00911                     case Virtex5::eRegisterLOUT:
00912                         oldColumnValue = currentColumnValue;
00913                         oldRowValue = currentRowValue;
00914                         oldTopValue = currentTopValue;
00915                         oldBlockValue = currentBlockValue;
00916                         currentColumnValue = (word & Virtex6::eFarMaskMajor);
00917                         currentRowValue = (word & Virtex6::eFarMaskRow);
00918                         currentTopValue = (word & Virtex6::eFarMaskTopBottom);
00919                         currentBlockValue = (word & Virtex6::eFarMaskBlockType);
00920                         newColumn = (currentColumnValue != oldColumnValue);
00921                         newRow = (currentRowValue != oldRowValue);
00922                         newTop = (currentTopValue != oldTopValue);
00923                         newBlock = (currentBlockValue != oldBlockValue);
00924                         os << ": " << Hex32(word);
00925                         if(newColumn) std::cout << "\t\t\t!!!New Column!!!";
00926                         if(newRow) std::cout << "\t\t\t$$$New Row$$$";
00927                         if(newTop) std::cout << "\t\t\t&&&New Top&&&";
00928                         if(newBlock) std::cout << "\t\t\t\t\t***New Block***" << Hex32(currentBlockValue);
00929                         break;
00930                     default:
00931                         // output the register contents
00932                         os << ": " << Hex32(word);
00933                         break;
00934                     }
00935 
00936                     os << std::endl;
00937                 }
00938 
00939             }
00940 
00941         }
00942 
00943         // return the stream reference
00944         return os;
00945     }
00946 
00947     // Virtex6 Output Stream
00948     std::ostream& operator <<(std::ostream& os, const Virtex6& rhs) {
00949         // insert the bitstream header
00950         os << static_cast<const Bitstream>(rhs) << std::endl;
00951         uint32_t cumulativeWordLength = 0;
00952 
00953         // iterate over the packets
00954         Virtex6::ERegister address = Virtex6::ERegister();
00955         VirtexPacketVector::const_iterator p = rhs.begin();
00956         VirtexPacketVector::const_iterator e = rhs.end();
00957         bool newColumn = false;
00958         bool newRow = false;
00959         bool newTop = false;
00960         bool newBlock = false;
00961         uint32_t oldColumnValue = 0;
00962         uint32_t oldRowValue = 0;
00963         uint32_t oldTopValue = 0;
00964         uint32_t oldBlockValue = 0;
00965         uint32_t currentColumnValue = 0;
00966         uint32_t currentRowValue = 0;
00967         uint32_t currentTopValue = 0;
00968         uint32_t currentBlockValue = 0;
00969         bool synchronized = false;
00970         while(p < e) {
00971 
00972             // insert the byte address
00973             os << "    " << Hex32(rhs.getHeaderByteLength() + (cumulativeWordLength << 2)) << ": ";
00974             // look up the packet
00975             const VirtexPacket& packet = *p++;
00976             cumulativeWordLength += packet.getWordSize();
00977 
00978             // catch bus sync words
00979             if(!synchronized) {
00980                 if(packet.isBusWidthSyncWord()) {
00981                     os << "BUS WIDTH SYNC" << std::endl;
00982                     continue;
00983                 } else if(packet.isBusWidthDetectWord()) {
00984                     os << "BUS WIDTH DETECT" << std::endl;
00985                     continue;
00986                 }
00987             }
00988 
00989             // handle dummy words
00990             if(packet.isDummyWord()) {
00991                 os << "DUMMY" << std::endl;
00992 
00993             // handle sync words
00994             } else if(packet.isSyncWord()) {
00995                 os << "SYNC" << std::endl;
00996 
00997             // handle reserved packets
00998             } else if(packet.isReserved()) {
00999                 os << Virtex6::sOpcodeName[packet.getOpcode()] << std::endl;
01000 
01001             // handle NOP packets
01002             } else if(packet.isNop()) {
01003                 int nops = 1;
01004                 while(p < e && p->isNop()) { nops++; p++; }
01005                 cumulativeWordLength += nops - 1;
01006                 os << "NOP x " << nops << std::endl;
01007 
01008             // handle regular type 1 or type 2 packets
01009             } else {
01010 
01011                 // look up the packet details
01012                 Virtex6::EPacketType type = packet.getType();
01013                 Virtex6::EOpcode opcode = packet.getOpcode();
01014                 uint32_t wordCount = packet.getWordCount();
01015                 const uint32_t word = packet[1];
01016                 // account for the packet type
01017                 os << Virtex6::sPacketTypeName[type];
01018                 switch(type) {
01019                 case Virtex6::ePacketType1: 
01020                     address = Virtex6::ERegister(packet.getAddress());
01021                     break;
01022                 case Virtex6::ePacketType2: 
01023                     break;
01024                 default: 
01025                     os << std::endl;
01026                     continue;
01027                 }
01028 
01029                 // handle read packets
01030                 if(opcode == packet.isRead()) {
01031                     os << " READ " << Virtex6::sRegisterName[address];
01032 
01033                 // handle write packets
01034                 } else if(opcode == Virtex6::eOpcodeWrite) {
01035                     os << " WRITE " << Virtex6::sRegisterName[address];
01036                     // process according to register address
01037                     switch(address) {
01038                     case Virtex6::eRegisterFDRI:
01039                         os << ": " << Hex32(wordCount) << " words";
01040                         break;
01041                     case Virtex6::eRegisterCMD: 
01042                         os << " " << Virtex6::sCommandName[word];
01043                         break;
01044                     case Virtex6::eRegisterCOR0:
01045                         os << ": " << Hex32(word);
01046                         Virtex6::writeSubfieldSettings(os, (uint32_t) word, Virtex6::sCOR0);
01047                         break;
01048                     case Virtex6::eRegisterCOR1:
01049                         os << ": " << Hex32(word);
01050                         Virtex6::writeSubfieldSettings(os, (uint32_t) word, Virtex6::sCOR1);
01051                         break;
01052                     case Virtex6::eRegisterSTAT:
01053                         os << ": " << Hex32(word);
01054                         Virtex6::writeSubfieldSettings(os, (uint32_t) word, Virtex6::sSTAT);
01055                         break;
01056                     case Virtex6::eRegisterCTL0:
01057                         os << ": " << Hex32(word);
01058                         Virtex6::writeSubfieldSettings(os, (uint32_t) word, Virtex6::sCTL0);
01059                         break;
01060                     case Virtex6::eRegisterCTL1:
01061                         os << ": " << Hex32(word);
01062                         Virtex6::writeSubfieldSettings(os, (uint32_t) word, Virtex6::sCTL1);
01063                         break;
01064                     case Virtex6::eRegisterMASK:
01065                         os << ": " << Hex32(word);
01066                         // we need to snoop the next packet, because the documented mask subfields 
01067                         // apply to CTL0 only, and not to CTL1 which is completely undefined
01068                         if(p < e) {
01069                             const VirtexPacket& nextPacket = *p;
01070                             if(nextPacket.isType1() && nextPacket.isWrite() 
01071                                 && nextPacket.getAddress() == Virtex6::eRegisterCTL1) {
01072                                 os << " ()";
01073                                 break;
01074                             }
01075                         }
01076                         Virtex6::writeSubfieldSettings(os, (uint32_t) word, Virtex6::sMASK0);
01077                         break;
01078                     case Virtex6::eRegisterWBSTAR:
01079                         os << ": " << Hex32(word);
01080                         Virtex6::writeSubfieldSettings(os, (uint32_t) word, Virtex6::sWBSTAR);
01081                         break;
01082                     case Virtex6::eRegisterTIMER:
01083                         os << ": " << Hex32(word);
01084                         Virtex6::writeSubfieldSettings(os, (uint32_t) word, Virtex6::sTIMER);
01085                         break;
01086                     // Added to make frame mapping debug easier
01087                     case Virtex6::eRegisterLOUT:
01088                         oldColumnValue = currentColumnValue;
01089                         oldRowValue = currentRowValue;
01090                         oldTopValue = currentTopValue;
01091                         oldBlockValue = currentBlockValue;
01092                         currentColumnValue = (word & Virtex6::eFarMaskMajor);
01093                         currentRowValue = (word & Virtex6::eFarMaskRow);
01094                         currentTopValue = (word & Virtex6::eFarMaskTopBottom);
01095                         currentBlockValue = (word & Virtex6::eFarMaskBlockType);
01096                         newColumn = (currentColumnValue != oldColumnValue);
01097                         newRow = (currentRowValue != oldRowValue);
01098                         newTop = (currentTopValue != oldTopValue);
01099                         newBlock = (currentBlockValue != oldBlockValue);
01100                         os << ": " << Hex32(word);
01101                         if(newColumn) std::cout << "\t\t\t!!!New Column!!!";
01102                         if(newRow) std::cout << "\t\t\t$$$New Row$$$";
01103                         if(newTop) std::cout << "\t\t\t&&&New Top&&&";
01104                         if(newBlock) std::cout << "\t\t\t\t\t***New Block***" << Hex32(currentBlockValue);
01105                         break;
01106                     default:
01107                         // output the register contents
01108                         os << ": " << Hex32(word);
01109                         break;
01110                     }
01111 
01112                     os << std::endl;
01113                 }
01114 
01115             }
01116 
01117         }
01118 
01119         // return the stream reference
01120         return os;
01121     }
01122 
01123     // Virtex7 Output Stream
01124     std::ostream& operator <<(std::ostream& os, const Virtex7& rhs) {
01125         // insert the bitstream header
01126         os << static_cast<const Bitstream>(rhs) << std::endl;
01127 
01128         // return the stream reference
01129         return os;
01130     }
01131 
01132 
01133 } // namespace bitstream
01134 } // namespace torc