TORC: torc/physical/DesignRegressionTest.cpp Source File

00001 // Torc - Copyright 2011 University of Southern California.  All Rights Reserved.
00002 // $HeadURL: https://svn.east.isi.edu/torc/trunk/src/torc/physical/DesignRegressionTest.cpp $
00003 // $Id: DesignRegressionTest.cpp 479 2011-06-05 04:04:54Z nsteiner $
00004 
00005 // This program is free software: you can redistribute it and/or modify it under the terms of the 
00006 // GNU General Public License as published by the Free Software Foundation, either version 3 of the 
00007 // License, or (at your option) any later version.
00008 // 
00009 // This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; 
00010 // without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See 
00011 // the GNU General Public License for more details.
00012 // 
00013 // You should have received a copy of the GNU General Public License along with this program.  If 
00014 // not, see <http://www.gnu.org/licenses/>.
00015 
00016 /// \file
00017 /// \brief Regression test for XDL Design class.
00018 
00019 #include <boost/test/unit_test.hpp>
00020 #include <boost/filesystem/convenience.hpp>
00021 #include "torc/common/DirectoryTree.hpp"
00022 #include "torc/physical/Factory.hpp"
00023 #include "torc/physical/XdlExporter.hpp"
00024 #include "torc/physical/OutputStreamHelpers.hpp"
00025 #include "torc/common/TestHelpers.hpp"
00026 #include <fstream>
00027 
00028 namespace torc {
00029 namespace physical {
00030 
00031 BOOST_AUTO_TEST_SUITE(physical)
00032 
00033 /// \brief Basic regression test for the entire XDL infrastructure.
00034 /// \details Note: This is neither a pleasant nor recommended way to create a design.
00035 BOOST_AUTO_TEST_CASE(DesignRegressionTest) {
00036 
00037     // determine whether or not to output additional debugging information; this serves primarily 
00038     // to show the user how certain design items can be accessed
00039     bool debug = false;
00040 
00041     // create a design
00042     DesignSharedPtr designPtr = Factory::newDesignPtr("blinker", "xc5vlx30", "ff324", "-1", "v3.2");
00043     designPtr->setConfig("_DESIGN_PROP", "P3_PLACE_OPTIONS", "EFFORT_LEVEL:high");
00044     designPtr->setConfig("_DESIGN_PROP", "", "P3_PLACED:");
00045     designPtr->setConfig("_DESIGN_PROP", "", "P3_PLACE_OPTIONS:");
00046     designPtr->setConfig("_DESIGN_PROP", "", "PK_NGMTIMESTAMP:1278102371");
00047     BOOST_CHECK_EQUAL(designPtr->getConfigCount(), 4u);
00048     if(debug) {
00049         ConfigMap::const_iterator p = designPtr->configBegin();
00050         ConfigMap::const_iterator e = designPtr->configEnd();
00051         while(p != e) {
00052             const std::string& setting = p->first;
00053             const Config& config = p->second;
00054             std::clog << "\t" << setting << ":" << config.getName() << ":" << config.getValue() 
00055                 << std::endl;
00056             p++;
00057         }
00058     }
00059 
00060     // create the modules (this design has no modules)
00061     // verify the expected module count
00062     BOOST_CHECK_EQUAL(designPtr->getModuleCount(), 0u);
00063     if(debug) {
00064         Design::ModuleSharedPtrConstIterator p = designPtr->modulesBegin();
00065         Design::ModuleSharedPtrConstIterator e = designPtr->modulesEnd();
00066         while(p != e) {
00067             const ModuleSharedPtr& modulePtr = *p++;
00068             std::clog << "\tmodule " << modulePtr->getName() << std::endl;
00069         }
00070     }
00071 
00072     // create the instances
00073     // instance clk
00074     InstanceSharedPtr clkInstPtr 
00075         = Factory::newInstancePtr("clk", "IOB", "CIOB_X17Y61", "B6", eInstanceBondingBonded);
00076     clkInstPtr->setConfig("IMUX", "", "I");
00077     clkInstPtr->setConfig("INBUF", "clk_ibuf/IBUFG", "");
00078     clkInstPtr->setConfig("PAD", "clk", "");
00079     clkInstPtr->setConfig("ISTANDARD", "", "LVCMOS25");
00080     designPtr->addInstance(clkInstPtr);
00081     // instance reset
00082     InstanceSharedPtr resetInstPtr 
00083         = Factory::newInstancePtr("reset", "IOB", "CIOB_X17Y59", "F11", eInstanceBondingBonded);
00084     resetInstPtr->setConfig("IMUX", "", "I");
00085     resetInstPtr->setConfig("INBUF", "reset_ibuf", "");
00086     resetInstPtr->setConfig("PAD", "reset", "");
00087     resetInstPtr->setConfig("ISTANDARD", "", "LVCMOS25");
00088     designPtr->addInstance(resetInstPtr);
00089     // instance out
00090     InstanceSharedPtr outInstPtr 
00091         = Factory::newInstancePtr("out", "IOB", "CIOB_X17Y59", "G11", eInstanceBondingBonded);
00092     outInstPtr->setConfig("OUSED", "", "0");
00093     outInstPtr->setConfig("OUTBUF", "out_obuf", "");
00094     outInstPtr->setConfig("PAD", "out", "");
00095     outInstPtr->setConfig("DRIVE", "", "12");
00096     outInstPtr->setConfig("OSTANDARD", "", "LVCMOS25");
00097     outInstPtr->setConfig("SLEW", "", "SLOW");
00098     designPtr->addInstance(outInstPtr);
00099     // instance clk_ibuf/BUFG
00100     InstanceSharedPtr clkIbufInstPtr 
00101         = Factory::newInstancePtr("clk_ibuf/BUFG", "BUFG", "CLK_BUFGMUX_X47Y44", "BUFGCTRL_X0Y30");
00102     clkIbufInstPtr->setConfig("BUFG", "clk_ibuf/BUFG", "");
00103     designPtr->addInstance(clkIbufInstPtr);
00104     // instance blink
00105     InstanceSharedPtr blinkInstPtr 
00106         = Factory::newInstancePtr("blink", "SLICEL", "CLBLL_X16Y59", "SLICE_X27Y59");
00107     blinkInstPtr->setConfig("CLKINV", "", "CLK");
00108     blinkInstPtr->setConfig("D6LUT", "blink_i", "#LUT:O6=~A6");
00109     blinkInstPtr->setConfig("DFF", "blink", "#FF");
00110     blinkInstPtr->setConfig("DFFINIT", "", "INIT0");
00111     blinkInstPtr->setConfig("DFFMUX", "", "O6");
00112     blinkInstPtr->setConfig("DFFSR", "", "SRLOW");
00113     blinkInstPtr->setConfig("SRUSED", "", "0");
00114     blinkInstPtr->setConfig("SYNC_ATTR", "", "SYNC");
00115     designPtr->addInstance(blinkInstPtr);
00116     // instance XDL_DUMMY_IOI_X17Y59_OLOGIC_X1Y118
00117     InstanceSharedPtr OLOGIC_X1Y118InstPtr 
00118         = Factory::newInstancePtr("XDL_DUMMY_IOI_X17Y59_OLOGIC_X1Y118", "OLOGIC", "IOI_X17Y59", 
00119         "OLOGIC_X1Y118");
00120     OLOGIC_X1Y118InstPtr->setConfig("_NO_USER_LOGIC", "", "");
00121     OLOGIC_X1Y118InstPtr->setConfig("_ROUTETHROUGH", "D1", "OQ");
00122     designPtr->addInstance(OLOGIC_X1Y118InstPtr);
00123     // instance XDL_DUMMY_IOI_X17Y59_ILOGIC_X1Y119
00124     InstanceSharedPtr ILOGIC_X1Y119InstPtr 
00125         = Factory::newInstancePtr("XDL_DUMMY_IOI_X17Y59_ILOGIC_X1Y119", "ILOGIC", "IOI_X17Y59", 
00126         "ILOGIC_X1Y119");
00127     ILOGIC_X1Y119InstPtr->setConfig("_NO_USER_LOGIC", "", "");
00128     ILOGIC_X1Y119InstPtr->setConfig("_ROUTETHROUGH", "D", "O");
00129     designPtr->addInstance(ILOGIC_X1Y119InstPtr);
00130     // instance XDL_DUMMY_IOI_X17Y61_ILOGIC_X1Y123
00131     InstanceSharedPtr ILOGIC_X1Y123InstPtr 
00132         = Factory::newInstancePtr("XDL_DUMMY_IOI_X17Y61_ILOGIC_X1Y123", "ILOGIC", "IOI_X17Y61", 
00133         "ILOGIC_X1Y123");
00134     ILOGIC_X1Y123InstPtr->setConfig("_NO_USER_LOGIC", "", "");
00135     ILOGIC_X1Y123InstPtr->setConfig("_ROUTETHROUGH", "D", "O");
00136     designPtr->addInstance(ILOGIC_X1Y123InstPtr);
00137     // verify that expected instance count
00138     BOOST_CHECK_EQUAL(designPtr->getInstanceCount(), 8u);
00139     if(debug) {
00140         Design::InstanceSharedPtrConstIterator p = designPtr->instancesBegin();
00141         Design::InstanceSharedPtrConstIterator e = designPtr->instancesEnd();
00142         while(p != e) {
00143             const InstanceSharedPtr& instancePtr = *p++;
00144             std::clog << "\tinstance " << instancePtr->getName() << std::endl;
00145         }
00146     }
00147 
00148     // create the nets
00149     // net blink
00150     NetSharedPtr blinkNetPtr = Factory::newNetPtr("blink");
00151     InstancePinSharedPtr blinkNetPin1Ptr = Factory::newInstancePinPtr(blinkInstPtr, "DQ");
00152     blinkNetPtr->addSource(blinkNetPin1Ptr);
00153     InstancePinSharedPtr blinkNetPin2Ptr = Factory::newInstancePinPtr(blinkInstPtr, "D6");
00154     blinkNetPtr->addSink(blinkNetPin2Ptr);
00155     InstancePinSharedPtr blinkNetPin3Ptr = Factory::newInstancePinPtr(outInstPtr, "O");
00156     blinkNetPtr->addSink(blinkNetPin3Ptr);
00157     blinkNetPtr->addPip(Factory::newPip("CLBLL_X16Y59", "L_DQ", "SITE_LOGIC_OUTS3", 
00158         ePipBidirectionalUnidirectionallyBuffered));
00159     blinkNetPtr->addPip(Factory::newPip("CLBLL_X16Y59", "SITE_IMUX_B47", "L_D6", 
00160         ePipBidirectionalUnidirectionallyBuffered));
00161     blinkNetPtr->addPip(Factory::newPip("INT_X16Y59", "EL2BEG2", "IMUX_B47", 
00162         ePipBidirectionalUnidirectionallyBuffered));
00163     blinkNetPtr->addPip(Factory::newPip("INT_X16Y59", "LOGIC_OUTS3", "EL2BEG2", 
00164         ePipBidirectionalUnidirectionallyBuffered));
00165     blinkNetPtr->addPip(Factory::newPip("INT_X17Y59", "EL2MID2", "IMUX_B41", 
00166         ePipBidirectionalUnidirectionallyBuffered));
00167     blinkNetPtr->addPip(Factory::newPip("IOI_X17Y59", "IOI_IMUX_B41", "IOI_O11", 
00168         ePipBidirectionalUnidirectionallyBuffered));
00169     blinkNetPtr->addPip(Factory::newPip("IOI_X17Y59", "IOI_O11", "IOI_O_PINWIRE1", 
00170         ePipBidirectionalUnidirectionallyBuffered, Factory::newRoutethroughPtr("_ROUTETHROUGH", 
00171         "D1", "OQ", OLOGIC_X1Y118InstPtr, "D1", "OQ")));
00172     blinkNetPtr->addPip(Factory::newPip("IOI_X17Y59", "IOI_O_PINWIRE1", "IOI_O1", 
00173         ePipBidirectionalUnidirectionallyBuffered));
00174     designPtr->addNet(blinkNetPtr);
00175     // net clk
00176     NetSharedPtr clkNetPtr = Factory::newNetPtr("clk");
00177     clkNetPtr->setConfig("_BELSIG", "PAD,PAD,clk", "clk");
00178     designPtr->addNet(clkNetPtr);
00179     // net clk_c
00180     NetSharedPtr clkCNetPtr = Factory::newNetPtr("clk_c");
00181     InstancePinSharedPtr clkCNetPin1Ptr = Factory::newInstancePinPtr(clkIbufInstPtr, "O");
00182     clkCNetPtr->addSource(clkCNetPin1Ptr);
00183     InstancePinSharedPtr clkCNetPin2Ptr = Factory::newInstancePinPtr(blinkInstPtr, "CLK");
00184     clkCNetPtr->addSink(clkCNetPin2Ptr);
00185     clkCNetPtr->addPip(Factory::newPip("CLBLL_X16Y59", "SITE_CLK_B0", "L_CLK", 
00186         ePipBidirectionalUnidirectionallyBuffered));
00187     clkCNetPtr->addPip(Factory::newPip("CLK_BUFGMUX_X47Y44", "CLK_BUFGMUX_POSTMUX_GCLKP30", 
00188         "CLK_BUFGMUX_GCLKP30", ePipBidirectionalUnidirectionallyBuffered));
00189     clkCNetPtr->addPip(Factory::newPip("CLK_HROW_X17Y49", "CLK_HROW_GCLK_BUF30", 
00190         "CLK_HROW_HCLKL_P5", ePipBidirectionalUnidirectionallyBuffered));
00191     clkCNetPtr->addPip(Factory::newPip("HCLK_X16Y49", "HCLK_G_HCLK_P5", "HCLK_LEAF_GCLK5", 
00192         ePipBidirectionalUnidirectionallyBuffered));
00193     clkCNetPtr->addPip(Factory::newPip("INT_X16Y59", "GCLK5", "CLK_B0", 
00194         ePipBidirectionalUnidirectionallyBuffered));
00195     designPtr->addNet(clkCNetPtr);
00196     // net clk_ibuf/IBUFG
00197     NetSharedPtr clkIibufIbufgNetPtr = Factory::newNetPtr("clk_ibuf/IBUFG");
00198     InstancePinSharedPtr clkIibufIbufgNetPin1Ptr = Factory::newInstancePinPtr(clkInstPtr, "I");
00199     clkIibufIbufgNetPtr->addSource(clkIibufIbufgNetPin1Ptr);
00200     InstancePinSharedPtr clkIibufIbufgNetPin2Ptr = Factory::newInstancePinPtr(clkIbufInstPtr, "I0");
00201     clkIibufIbufgNetPtr->addSink(clkIibufIbufgNetPin2Ptr);
00202     clkIibufIbufgNetPtr->addPip(Factory::newPip("CLK_BUFGMUX_X47Y44", 
00203         "CLK_BUFGMUX_MUXED_IN_CLKT_P28", "CLK_BUFGMUX_PREMUX0_CLK30", 
00204         ePipBidirectionalUnidirectionallyBuffered));
00205     clkIibufIbufgNetPtr->addPip(Factory::newPip("CLK_BUFGMUX_X47Y44", "CLK_BUFGMUX_PREMUX0_CLK30", 
00206         "CLK_BUFGMUX_CLKP0_30", ePipBidirectionalUnidirectionallyBuffered));
00207     clkIibufIbufgNetPtr->addPip(Factory::newPip("CLK_IOB_T_X17Y60", "CLK_IOB_CLK_BUF1", 
00208         "CLK_IOB_MUXED_CLKOUT28", ePipBidirectionalUnidirectionallyBuffered));
00209     clkIibufIbufgNetPtr->addPip(Factory::newPip("CLK_IOB_T_X17Y60", "CLK_IOB_PAD_CLK1", 
00210         "CLK_IOB_CLK_BUF1", ePipBidirectionalUnidirectionallyBuffered));
00211     clkIibufIbufgNetPtr->addPip(Factory::newPip("IOI_X17Y61", "IOI_D0", "IOI_I0", 
00212         ePipBidirectionalUnidirectionallyBuffered, Factory::newRoutethroughPtr("_ROUTETHROUGH", 
00213         "D", "O", ILOGIC_X1Y123InstPtr, "D", "O")));
00214     clkIibufIbufgNetPtr->addPip(Factory::newPip("IOI_X17Y61", "IOI_I0", "IOI_I_2GCLK0", 
00215         ePipBidirectionalUnidirectionallyBuffered));
00216     clkIibufIbufgNetPtr->addPip(Factory::newPip("IOI_X17Y61", "IOI_IBUF0", "IOI_D0", 
00217         ePipBidirectionalUnidirectionallyBuffered));
00218     designPtr->addNet(clkIibufIbufgNetPtr);
00219     // net out
00220     NetSharedPtr outNetPtr = Factory::newNetPtr("out");
00221     outNetPtr->setConfig("_BELSIG", "PAD,PAD,out", "out");
00222     designPtr->addNet(outNetPtr);
00223     // net reset
00224     NetSharedPtr resetNetPtr = Factory::newNetPtr("reset");
00225     resetNetPtr->setConfig("_BELSIG", "PAD,PAD,reset", "reset");
00226     designPtr->addNet(resetNetPtr);
00227     // net reset_c
00228     NetSharedPtr resetCNetPtr = Factory::newNetPtr("reset_c");
00229     InstancePinSharedPtr resetCNetPin1Ptr = Factory::newInstancePinPtr(resetInstPtr, "I");
00230     resetCNetPtr->addSource(resetCNetPin1Ptr);
00231     InstancePinSharedPtr resetCNetPin2Ptr = Factory::newInstancePinPtr(blinkInstPtr, "SR");
00232     resetCNetPtr->addSink(resetCNetPin2Ptr);
00233     resetCNetPtr->addPip(Factory::newPip("CLBLL_X16Y59", "SITE_CTRL_B2", "L_SR", 
00234         ePipBidirectionalUnidirectionallyBuffered));
00235     resetCNetPtr->addPip(Factory::newPip("INT_INTERFACE_X17Y59", "INT_INTERFACE_LOGIC_OUTS_B11", 
00236         "INT_INTERFACE_LOGIC_OUTS11", ePipBidirectionalUnidirectionallyBuffered));
00237     resetCNetPtr->addPip(Factory::newPip("INT_X16Y59", "CTRL2", "CTRL_B2", 
00238         ePipBidirectionalUnidirectionallyBuffered));
00239     resetCNetPtr->addPip(Factory::newPip("INT_X16Y59", "WS2MID2", "CTRL2", 
00240         ePipBidirectionalUnidirectionallyBuffered));
00241     resetCNetPtr->addPip(Factory::newPip("INT_X17Y59", "LOGIC_OUTS11", "WS2BEG2", 
00242         ePipBidirectionalUnidirectionallyBuffered));
00243     resetCNetPtr->addPip(Factory::newPip("IOI_X17Y59", "IOI_D0", "IOI_I0", 
00244         ePipBidirectionalUnidirectionallyBuffered, Factory::newRoutethroughPtr("_ROUTETHROUGH", 
00245         "D", "O", ILOGIC_X1Y119InstPtr, "D", "O")));
00246     resetCNetPtr->addPip(Factory::newPip("IOI_X17Y59", "IOI_I0", "IOI_LOGIC_OUTS11", 
00247         ePipBidirectionalUnidirectionallyBuffered));
00248     resetCNetPtr->addPip(Factory::newPip("IOI_X17Y59", "IOI_IBUF0", "IOI_D0", 
00249         ePipBidirectionalUnidirectionallyBuffered));
00250     designPtr->addNet(resetCNetPtr);
00251     // verify the expected net count
00252     BOOST_CHECK_EQUAL(designPtr->getNetCount(), 7u);
00253     if(debug) {
00254         Design::NetSharedPtrConstIterator p = designPtr->netsBegin();
00255         Design::NetSharedPtrConstIterator e = designPtr->netsEnd();
00256         while(p != e) {
00257             const NetSharedPtr& netPtr = *p++;
00258             std::clog << "\tnet " << netPtr->getName() << std::endl;
00259         }
00260     }
00261 
00262     // create the appropriate file paths
00263     boost::filesystem::path regressionPath 
00264         = torc::common::DirectoryTree::getExecutablePath() / "regression";
00265     boost::filesystem::path generatedPath = regressionPath / "DesignUnitTest.generated.xdl";
00266     boost::filesystem::path referencePath = regressionPath / "DesignUnitTest.reference.xdl";
00267     // export the created design
00268     std::fstream xdlExport(generatedPath.string().c_str(), std::ios_base::out);
00269     XdlExporter fileExporter(xdlExport);
00270     fileExporter(designPtr);
00271 
00272     // compare the reference and generated XDL
00273     BOOST_CHECK(torc::common::fileContentsAreEqual(generatedPath, referencePath));
00274 
00275 }
00276 
00277 BOOST_AUTO_TEST_SUITE_END()
00278 
00279 } // namespace physical
00280 } // namespace torc
00281 
00282 #if 0
00283 /*
00284 
00285 # =======================================================
00286 # XDL NCD CONVERSION MODE $Revision: 1.01$
00287 # time: Fri Jul  2 18:17:55 2010
00288 
00289 # =======================================================
00290 
00291 
00292 # =======================================================
00293 # The syntax for the design statement is:                
00294 # design <design_name> <part> <ncd version>;             
00295 # or                                                     
00296 # design <design_name> <device> <package> <speed> <ncd_version>
00297 # =======================================================
00298 design "blinker" xc5vlx30ff324-1 v3.2 ,
00299   cfg "
00300        _DESIGN_PROP:P3_PLACE_OPTIONS:EFFORT_LEVEL:high
00301        _DESIGN_PROP::P3_PLACED:
00302        _DESIGN_PROP::P3_PLACE_OPTIONS:
00303        _DESIGN_PROP::PK_NGMTIMESTAMP:1278102371";
00304 
00305 
00306 #  =======================================================
00307 #  The syntax for instances is:
00308 #      instance <name> <sitedef>, placed <tile> <site>, cfg <string> ;
00309 #  or
00310 #      instance <name> <sitedef>, unplaced, cfg <string> ;
00311 # 
00312 #  For typing convenience you can abbreviate instance to inst.
00313 # 
00314 #  For IOs there are two special keywords: bonded and unbonded
00315 #  that can be used to designate whether the PAD of an unplaced IO is
00316 #  bonded out. If neither keyword is specified, bonded is assumed.
00317 # 
00318 #  The bonding of placed IOs is determined by the site they are placed in.
00319 # 
00320 #  If you specify bonded or unbonded for an instance that is not an
00321 #  IOB it is ignored.
00322 # 
00323 #  Shown below are three examples for IOs. 
00324 #     instance IO1 IOB, unplaced ;          # This will be bonded
00325 #     instance IO1 IOB, unplaced bonded ;   # This will be bonded
00326 #     instance IO1 IOB, unplaced unbonded ; # This will be unbonded
00327 #  =======================================================
00328 inst "clk" "IOB",placed CIOB_X17Y61 B6  ,
00329   cfg " DIFFI_INUSED::#OFF DIFF_TERM::#OFF IMUX::I OUSED::#OFF PADOUTUSED::#OFF
00330        PULLTYPE::#OFF TUSED::#OFF INBUF:clk_ibuf/IBUFG: PAD:clk:
00331          ISTANDARD::LVCMOS25 "
00332   ;
00333 inst "reset" "IOB",placed CIOB_X17Y59 F11  ,
00334   cfg " DIFFI_INUSED::#OFF DIFF_TERM::#OFF IMUX::I OUSED::#OFF PADOUTUSED::#OFF
00335        PULLTYPE::#OFF TUSED::#OFF INBUF:reset_ibuf: PAD:reset:
00336          ISTANDARD::LVCMOS25 "
00337   ;
00338 inst "out" "IOB",placed CIOB_X17Y59 G11  ,
00339   cfg " DIFFI_INUSED::#OFF DIFF_TERM::#OFF IMUX::#OFF OUSED::0 PADOUTUSED::#OFF
00340        PULLTYPE::#OFF TUSED::#OFF OUTBUF:out_obuf: PAD:out:
00341          DRIVE::12  OSTANDARD::LVCMOS25  SLEW::SLOW "
00342   ;
00343 inst "clk_ibuf/BUFG" "BUFG",placed CLK_BUFGMUX_X47Y44 BUFGCTRL_X0Y30  ,
00344   cfg " BUFG:clk_ibuf/BUFG: "
00345   ;
00346 inst "blink" "SLICEL",placed CLBLL_X16Y59 SLICE_X27Y59  ,
00347   cfg " A5LUT::#OFF A6LUT::#OFF ACY0::#OFF AFF::#OFF AFFINIT::#OFF AFFMUX::#OFF
00348        AFFSR::#OFF AOUTMUX::#OFF AUSED::#OFF B5LUT::#OFF B6LUT::#OFF BCY0::#OFF
00349        BFF::#OFF BFFINIT::#OFF BFFMUX::#OFF BFFSR::#OFF BOUTMUX::#OFF BUSED::#OFF
00350        C5LUT::#OFF C6LUT::#OFF CCY0::#OFF CEUSED::#OFF CFF::#OFF CFFINIT::#OFF
00351        CFFMUX::#OFF CFFSR::#OFF CLKINV::CLK COUTMUX::#OFF COUTUSED::#OFF
00352        CUSED::#OFF D5LUT::#OFF D6LUT:blink_i:#LUT:O6=~A6 DCY0::#OFF DFF:blink:#FF
00353        DFFINIT::INIT0 DFFMUX::O6 DFFSR::SRLOW DOUTMUX::#OFF DUSED::#OFF
00354        PRECYINIT::#OFF REVUSED::#OFF SRUSED::0 SYNC_ATTR::SYNC "
00355   ;
00356 inst "XDL_DUMMY_IOI_X17Y59_OLOGIC_X1Y118" "OLOGIC",placed IOI_X17Y59 OLOGIC_X1Y118  ,
00357   cfg "_NO_USER_LOGIC::  _ROUTETHROUGH:D1:OQ "
00358   ;
00359 inst "XDL_DUMMY_IOI_X17Y59_ILOGIC_X1Y119" "ILOGIC",placed IOI_X17Y59 ILOGIC_X1Y119  ,
00360   cfg "_NO_USER_LOGIC::  _ROUTETHROUGH:D:O "
00361   ;
00362 inst "XDL_DUMMY_IOI_X17Y61_ILOGIC_X1Y123" "ILOGIC",placed IOI_X17Y61 ILOGIC_X1Y123  ,
00363   cfg "_NO_USER_LOGIC::  _ROUTETHROUGH:D:O "
00364   ;
00365 
00366 #  ================================================
00367 #  The syntax for nets is:
00368 #     net <name> <type>,
00369 #       outpin <inst_name> <inst_pin>,
00370 #       .
00371 #       .
00372 #       inpin <inst_name> <inst_pin>,
00373 #       .
00374 #       .
00375 #       pip <tile> <wire0> <dir> <wire1> , # [<rt>]
00376 #       .
00377 #       .
00378 #       ;
00379 # 
00380 #  There are three available wire types: wire, power and ground.
00381 #  If no type is specified, wire is assumed.
00382 # 
00383 #  Wire indicates that this a normal wire.
00384 #  Power indicates that this net is tied to a DC power source.
00385 #  You can use "power", "vcc" or "vdd" to specify a power net.
00386 # 
00387 #  Ground indicates that this net is tied to ground.
00388 #  You can use "ground", or "gnd" to specify a ground net.
00389 # 
00390 #  The <dir> token will be one of the following:
00391 # 
00392 #     Symbol Description
00393 #     ====== ==========================================
00394 #       ==   Bidirectional, unbuffered.
00395 #       =>   Bidirectional, buffered in one direction.
00396 #       =-   Bidirectional, buffered in both directions.
00397 #       ->   Directional, buffered.
00398 # 
00399 #  No pips exist for unrouted nets.
00400 #  ================================================
00401 net "blink" , 
00402   outpin "blink" DQ ,
00403   inpin "blink" D6 ,
00404   inpin "out" O ,
00405   pip CLBLL_X16Y59 L_DQ -> SITE_LOGIC_OUTS3 , 
00406   pip CLBLL_X16Y59 SITE_IMUX_B47 -> L_D6 , 
00407   pip INT_X16Y59 EL2BEG2 -> IMUX_B47 , 
00408   pip INT_X16Y59 LOGIC_OUTS3 -> EL2BEG2 , 
00409   pip INT_X17Y59 EL2MID2 -> IMUX_B41 , 
00410   pip IOI_X17Y59 IOI_IMUX_B41 -> IOI_O11 , 
00411   pip IOI_X17Y59 IOI_O11 -> IOI_O_PINWIRE1 ,  #  _ROUTETHROUGH:D1:OQ "XDL_DUMMY_IOI_X17Y59_OLOGIC_X1Y118" D1 -> OQ
00412   pip IOI_X17Y59 IOI_O_PINWIRE1 -> IOI_O1 , 
00413   ;
00414 net "clk" , cfg " _BELSIG:PAD,PAD,clk:clk",
00415   ;
00416 net "clk_c" , 
00417   outpin "clk_ibuf/BUFG" O ,
00418   inpin "blink" CLK ,
00419   pip CLBLL_X16Y59 SITE_CLK_B0 -> L_CLK , 
00420   pip CLK_BUFGMUX_X47Y44 CLK_BUFGMUX_POSTMUX_GCLKP30 -> CLK_BUFGMUX_GCLKP30 , 
00421   pip CLK_HROW_X17Y49 CLK_HROW_GCLK_BUF30 -> CLK_HROW_HCLKL_P5 , 
00422   pip HCLK_X16Y49 HCLK_G_HCLK_P5 -> HCLK_LEAF_GCLK5 , 
00423   pip INT_X16Y59 GCLK5 -> CLK_B0 , 
00424   ;
00425 net "clk_ibuf/IBUFG" , 
00426   outpin "clk" I ,
00427   inpin "clk_ibuf/BUFG" I0 ,
00428   pip CLK_BUFGMUX_X47Y44 CLK_BUFGMUX_MUXED_IN_CLKT_P28 -> CLK_BUFGMUX_PREMUX0_CLK30 , 
00429   pip CLK_BUFGMUX_X47Y44 CLK_BUFGMUX_PREMUX0_CLK30 -> CLK_BUFGMUX_CLKP0_30 , 
00430   pip CLK_IOB_T_X17Y60 CLK_IOB_CLK_BUF1 -> CLK_IOB_MUXED_CLKOUT28 , 
00431   pip CLK_IOB_T_X17Y60 CLK_IOB_PAD_CLK1 -> CLK_IOB_CLK_BUF1 , 
00432   pip IOI_X17Y61 IOI_D0 -> IOI_I0 ,  #  _ROUTETHROUGH:D:O "XDL_DUMMY_IOI_X17Y61_ILOGIC_X1Y123" D -> O
00433   pip IOI_X17Y61 IOI_I0 -> IOI_I_2GCLK0 , 
00434   pip IOI_X17Y61 IOI_IBUF0 -> IOI_D0 , 
00435   ;
00436 net "out" , cfg " _BELSIG:PAD,PAD,out:out",
00437   ;
00438 net "reset" , cfg " _BELSIG:PAD,PAD,reset:reset",
00439   ;
00440 net "reset_c" , 
00441   outpin "reset" I ,
00442   inpin "blink" SR ,
00443   pip CLBLL_X16Y59 SITE_CTRL_B2 -> L_SR , 
00444   pip INT_INTERFACE_X17Y59 INT_INTERFACE_LOGIC_OUTS_B11 -> INT_INTERFACE_LOGIC_OUTS11 , 
00445   pip INT_X16Y59 CTRL2 -> CTRL_B2 , 
00446   pip INT_X16Y59 WS2MID2 -> CTRL2 , 
00447   pip INT_X17Y59 LOGIC_OUTS11 -> WS2BEG2 , 
00448   pip IOI_X17Y59 IOI_D0 -> IOI_I0 ,  #  _ROUTETHROUGH:D:O "XDL_DUMMY_IOI_X17Y59_ILOGIC_X1Y119" D -> O
00449   pip IOI_X17Y59 IOI_I0 -> IOI_LOGIC_OUTS11 , 
00450   pip IOI_X17Y59 IOI_IBUF0 -> IOI_D0 , 
00451   ;
00452 
00453 # =======================================================
00454 # SUMMARY
00455 # Number of Module Defs: 0
00456 # Number of Module Insts: 0
00457 # Number of Primitive Insts: 5
00458 # Number of Nets: 7
00459 # =======================================================
00460 */
00461 #endif